1. Field of the Invention
The present invention relates to a serial control device such as a clock synchronous serial interface.
2. Description of Related Art
In serial communication, it is necessary to change the length of one frame depending on a device at the other end of communication.
U.S. Pat. No. 5,454,097 (which is referred to hereinafter as the patent document 1), for example, discloses a serial control device including a plurality of serial control blocks. FIG. 12 shows a configuration of the serial control device disclosed in the patent document 1. The serial control device aims to write data with a variable frame bit length into a serial device.
Specifically, in FIG. 12, a cascaded peripheral device (serial control device) 10 includes at least two registers 51, 52 and 53 with different sizes. Input data is consecutively shifted through a shift register 40 simultaneously by a clock signal. Serial output of the shift register 40 is output from a data output terminal 18 of the cascaded peripheral device 10.
A counter 20 increments its state in response to a clock signal. When the counter 20 corresponds to one of the registers 51, 52 and 53 and a data signal becomes disabled, decoders 30, 31, 32, 33 and 35 activates one of load signals in response to the state of the counter 20.
Upon reaching a maximum value corresponding to the size of the shift register 40, the counter 20 is reset so that the counter 20 becomes disabled in response to the data signal.
In the configuration of FIG. 12, other peripheral devices 60 and 70 are cascaded to the peripheral device 10. If a frame bit length exceeds the size of the shift register 40, data is written to a serial device by using the peripheral devices 60 and 70. After data with the frame bit length is written to a plurality of peripheral devices, data transfer is performed. In this manner, data transfer according to the frame bit length is implemented.
Further, MPC5553/5554 Microcontroller Reference Manual Rev. 4.0, Freescale Semiconductor, 2007 April, pp. 914-916 (20-48-20-50) (which is referred to hereinafter as “PC5553/5554 Microcontroller Reference Manual”) discloses a configuration of another serial control device. FIGS. 13 and 14 show the configuration of the serial control device disclosed in MPC5553/5554 Microcontroller Reference Manual. The serial control device permits transfer of a DSI frame. The DSI frame is made up of bits in which a plurality of serially cascaded DSIPs are connected. The connected frames contain 8 to 64 bits.
FIGS. 13 and 14 show the configuration in MPC5554/5553. In MPC5554 (master), SOUT of DSPI_A is connected to SIN of DSPI_B (slave). In MPC5553 (master), SOUT of DSPI_B is connected to SIN of DSPI_C (slave).
In MPC5554, SOUT of DSPI_B (slave) is connected to SIN of DSPI_C (slave) or the like. In MPC5553, SOUT of DSPI_C (slave) is connected to SIN of DSPI_D (slave) or the like.
SOUT of on-chip DSPI slave is connected to SIN of external SPI slave. SOUT of external SPI slave is connected to SIN of DSPI_A master (MPC5554)/DSPI_B (MPC5553).
MPC5554 DSPI_A master and MPC5553 DSPI_B master control the entire transfer. Slave DSIPs start transfer, and uses a trigger output signal MTRIG in order to notify DSPI_A (MPC5554)/DSPI_B master (MPC5553) that a trigger condition has occurred.
MPC5554 DSPI_A master and MPC5553 DSPI_B master start transfer when there are consecutive data rows exist in the on-chip DSPI slave. Further, DSPI masters receive the MTRIG signal. When DSPI slave sends out a ht signal, a trigger signal (MTRIG signal) is sent out from another DSPI slave to the DSPI master.
An MTOCNT field in DSPIx_DSICR sets the number of bits to be transferred. It is necessary that the MTOCNT field corresponds to the sum of all FMSZ fields regarding DSPIx_CTARs that are selected for DSPI master and all DSPI slaves.
In some cases, a serial peripheral device needs to transmit or receive a frame longer than the data bus width of a CPU (Central Processing Unit) with a frame length of 24 bits, 32 bits, 48 bits or the like. Further, in MPC5554 DSPI_A master and MPC5553 DSPI_B master, a framing error can occur when serial data contained in one frame is not transferred (serially communicated) within a given length of time. For example, an error can occur when data transfer of the next bit takes longer than a given length of time after data transfer of the CPU data bus width. In such a case, data transfer of different frame lengths have been implemented by connecting a plurality of serial control devices in a cascaded manner in the configurations disclosed in the patent document 1 and MPC5553/5554 Microcontroller Reference Manual.
One reason is that functions are allocated to the respective terminals included in a package. To be specific, doubled functions such as a serial control device and a timer device are allocated in a single-chip microcomputer, and a QFP (Quad Flat Package) package with a relatively small number of pins such as 64 pins to 176 pins is often used in consideration of easiness of packaging and package costs. A function of another peripheral device is allocated to a terminal different from the one used for an intended peripheral device. Therefore, when adding a serial control device, although it is necessary to allocate a terminal of the serial control device to a terminal different from the one allocated to the first serial control device, another terminal is already allocated to the terminal, thus failing to work out as a set.